The lower layer of communication networks like the connectivity layer in a core network of a cellular environment could be seen as a layer of distributed resources for managing data flows. Switches and multiplexers are some of the main components for this purpose. In complex communication networks managing data of different formats and varying data rates, it is of great importance that the construction of the components is flexible without being too complex.
Conventionally, the switches comprise a number of serial inputs and outputs. The data stream of one input may be directed in its entirety to a certain output line, or it may consist of a mixture of time division multiplexed data frames that are to be distributed to several outputs. The different lines may be running various interfaces e.g. E1, E2, E3 and STM-1 (FIG. 1). Additionally, the data speed of each input line may vary in a wide range. The transition of data frames in the switches is often executed by means of time slot buses located on the back plane of the switches.
A variant of such a switch is illustrated in FIG. 2. In this example switch, there are up to 32 serial input lines and 32 serial output lines. To make the switch flexible and useful for a number of purposes, the possible data speed of each line should vary in a wide range e.g. from 8 kbit/s up to 45 Mbit/s. The transition of data is executed on one or more fast TDM buses, transporting the data frames on time slots preferably with a minimum delay.
To avoid bit slips on bit pipes through the switch, the nominal output bit-rate has to be the same as the nominal input bit-rate. A bit pipe is a serial bit stream (for instance 2 Mbit) coming in at a receiving line, transmitted over the TDM bus and out on a transmitting line (same nominal speed, i.e. 2 Mbit/s). It is not possible to transmit data with the data clocks. This means that the input bit-rate has to be regenerated on the output.
Since the receiving lines are independent in relation to data speed and timing, it is also a challenge to transmit data on the same data bus without introducing data and timing faults. At the same time, the memory requirements due to speed inconsistency should not be unreasonable high.
Also, requirements on maximum tolerable input jitter, jitter attenuation and maximum intrinsic jitter have to be met.
Regenerating the input bit rate on the output may be done by introducing a FIFO-FLL solution. FIFO (First In First Out) fill degree limits are defined, and the FLL then tries to lock the output frequency so that the FIFO fill degree is between an upper and lower limit or as close as possible to an ideal limit.
In FIG. 3, DATA_IN is latched/clocked into the FIFO by the signal WRITE. Data is read out of the FIFO (DATA_OUT) by the signal READ coming from the FLL. TX_CLK is the output (transmit) data clock and will be in phase with DATA_OUT. An example of such a solution may be seen in [2].
When the FIFO fill degree goes above the “upper limit” defined, the signal INCR indicates to the FLL that the output frequency has to be increased. When the FIFO fill degree goes below the “lower limit”, the signal DECR indicates to the FLL that the output frequency has to be decreased. The FLL may be implemented as a PI-regulator.
A lot of other solutions using the FIFO fill degree for regenerating a transmit data clock exist. The following patents include such solutions.
U.S. Pat. No. 5,708,686
U.S. Pat. No. 5,898,744
U.S. Pat. No. 6,172,964
Canadian patent CA-2019649 A
Problems with Known Solutions
An I-component has to be implemented in the regulator to achieve more regulation the longer the FIFO fill degree is outside the limits. A P-component has to be implemented to make the regulator stable. The disadvantages with such a PI-regulator are:
The I-component can make the FLL unstable. The higher the I-component is related to the P component, the more unstable the regulator becomes.
The I-component makes the FLL slow. To get the FLL locked often takes several seconds when the jitter attenuation requirements shall be met.
Complicated logic for making the in-lock time shorter may be necessary.
Jitter attenuation requirements limit the size of the P-component.
Intrinsic jitter is introduced by both the I-component and the P-component, but mostly by the I-component.
The main drawbacks with the inventions described in the U.S. and Canadian patents mentioned above are related to the frequency generation and to the phase error modulation onto a nominal frequency.
U.S. Pat. No. 5,708,686 uses voltage-controlled oscillators to cover a large frequency range. The output clock is generated by a frequency divider and not a frequency multiplier, a half full signal is needed and the readout-clock must have a lower frequency than the receive clock.
U.S. Pat. No. 5,898,744 uses a numerically controlled oscillator to generate the output clock. The number of output frequencies is then very limited. In the detailed description of the figures, only two frequencies may be generated (line 6-15).
In U.S. Pat. No. 6,172,964, a device to control a mark-space ratio is necessary. The way the output frequency is generated in claim means that it is generated by a frequency divider, as described at line 4-3 to 4-8, and not a frequency multiplier. This leads to short frequency jumps to frequencies that differ relatively much from the nominal frequency (example of 651 ppm as described at line 4-17). Such frequency jumps introduce wander in the system. The way to minimize jitter explained in line 3-53 to 3-56 really just pulls the jitter down in the frequency domain and instead introduces a lot of wander. This is a problem since wander is more difficult to attenuate than jitter. This invention is preferably used in an ATM network and not in a TDM system (line 2-34).
In Canadian patent CA-2019649 A, the concept with the FIFO-FLL solution is used as part of a more comprehensive invention, but the details of how the frequency locked loop are implemented are not described.
The FIFO solutions require that some timing and fault information is transmitted together with the data from the receiving to the transmitting side, and a certain frame structure must be used.
In this context, Canadian patent CA-2019649 A uses multi-frame. Time variance compensating information is transferred in a side channel located in some fixed bit positions in the multiframe. This is best suited for low bit rates (below 64 kbit/s) and over a low speed TDM bus (i.e. 2 Mbit/s).
Besides, the side channel for transferring timing information has a fixed bandwidth, and the multiframe structure is quite complicated.
Because of the multiframe structure, timing information can not be updated for each frame.
The way the RX FIFO-Digital FLL solution uses threshold values to control the rate of the output clock does not give optimal jitter and stability characteristics on the output frequency.
Generally, problems with the known way of signalling timing faults described in the chapter above is that since the CPU must be involved, the action may be relatively long lasting and some of the CPU capacities become occupied.